The Kibra 380 is the first standalone DDR3 bus analyzer designed specifically to overcome the cost and complexity of monolithic test approaches that rely on logic analyzer platforms. Fully self-contained, the Kibra 380 uses non-intrusive interposer probes to transparently monitor DDR3 transactions on a live system. With no calibration required, the Kibra 380 provides complete visibility to DDR3 command and timing intervals allowing developers to verify compliance with the JEDEC specification.

The newest DDR memory interface technology, DDR3, offers significant advantages over previous DDR generations. DDR3 supports data rates up to 1600 Mbps per pin with an operating voltage of 1.5 volts, a 17% reduction from the previous generation of DDR2, which operates at 1.8 volts. DDR3’s built-in power conservation features, like partial refresh are desirable for mobile applications where battery power will no longer be needed just to refresh a portion of the DRAM not in active use. DDR3 also has a specification for an optional thermal sensor that allow mobile engineers to save further power by providing minimum refresh cycles.

Since DDR3 is designed to run at higher memory speeds the signal integrity of the memory module is now more important. DDR3 uses “fly-by” routing instead of the “T branches” seen on DDR2 modules. This means the address and control lines are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on DDR2 modules. “Fly-by” takes away the mechanical line balancing and uses automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data. DDR3 also uses more internal banks – 8 instead of the 4 used by DDR2 – to further speed up the system. More internal banks allow advance prefetch to reduce access latency.

All DDR memory access are burst oriented where an access starts at a selected location and continues for the burst amount. As an added complexity, Intel memory design uses interleaved burst type; with most other controllers using sequential burst type. The ability to distinguish between interleaved and sequential bursts during testing is a critical distinction when triggering on timing violations. Other complexities introduced with DDR3 include signal integrity testing on the Data lines. Because DQ/DQS are bidirectional, developers must use the DQ/DQS relationships to distinguish between Read / Write operations on the bus. Teledyne LeCroy’s Kibra analyzer helps address this test challenge using dedicated, low latency SMA trigger-out to a scope for Read and Write operations (WE).

Demand from real time system developers will continue to push the evolution of memory to meet the need for improved performance, density and power efficiency.


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Rated Speed 800-1600 Mbps
Vdd/Vddq 1.5V +/- 0.075V
Internal Banks 8
Termination All DQ signals
Topology Fly-by
Driver Control Self Calibration with ZQ
Thermal Sensor Yes (Optional)